This year, the workshop focuses on Fan-out Package. Fan-out Packages are getting significant momentum as fine pitch, small form-factor, and heterogeneous integration solutions.
The application of Fan-out Package is expanding rapidly, ranging from small devices to high-end mobile processors and SiP modules.
High yielding integration of Fan-out Package is requiring innovative breakthroughs in all areas including IC chip design, RDL fabrication, measurement and inspection, and verification tools. Equipment and materials are key elements to be innovated.
Close collaboration among industry, universities, and research institutes is crucial to resolve those challenges.
The organizers of the workshop have invited leading experts from diverse sites to share their expertise and experiences with others who need guidance and advice.
You are cordially invited to the forum of informative lecture and open discussion with leaders in this field.
Young-Hyun Jun (President, Semiconductor Society, IEIE)
Joonghwee Cho (Vice President, Semiconductor Society, IEIE)
Jinsang Kim (Workshop Organizer)
Tae-Je Cho (Workshop Organizer)
O Title : Fan-out Package Workshop 2017
|08:55-09:00||Opening||Young-Hyun Jun, President
(The Semiconductor Society, IEIE)
|Session-1 : Trends and Market|
|09:00-09:40||Fanout Package; Opportunities and Challenges||Choon Heung Lee
(President, LAM Research)
|09:40-10:10||Market and Technology Trends in Fan-out Packaging||Santosh Kumar
(Dir. of 3DIC,Yole)
|10:30-11:00||Design Methodology for Fanout Packaging||Jae-Ho Lee
|11:00-11:30||Research and Development for Fanout Packaging||Eric Beyne
|11:30-12:00||High-density multi RDL layers Enabled by Excimer Laser Dual Damascene Process for Wafer and Panel Level Packaging||Matthew Gingerella
|12:00-13:10||Lunch & Social|
|Session-2 : Technology Development|
|13:10-13:40||WLP, FO-WLP PID Development||Takuji Ikeda
|13:40-14:10||Encapsulation Materials for Fanout||Ikeuchi Takatoshi
|14:10-14:40||Measurement Technology for fan-out packages||Motozuna Masamichi
|14:40-15:10||PVD and Dry Etch Process Solutions for Fan Out Packages||David Butler
(EVP, Prouduct Management
and Marketing, SPTS)
|15:30-16:00||Temparory Bonding, Debonding Technology||Otaka Shoji
|16:00-16:30||Recent Advances and Trends in fan-out Packaging Technology||Won-Chul Do
|16:30-17:00||Advanced eWLP FOWLP: Enabling Integrated Packaging Solutions||Seung-Wook Yoon
(Dir. Technical Marketing, Statschippac)
|17:00-17:10||Closing||Prof. Joonghwee Cho,
(The Semiconductor Society, IEIE)
o 사전등록: 2017년 9월 25일(월) 까지
o 입금계좌: 186-00027-241 한국씨티은행
o 예금주: 대한전자공학회
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Electronics & Information Building (2F),
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경희대학교 국제캠퍼스(수원) 전자정보대학, 2층 (205호)
From Gyeongbu Express Way
-> Suwon Exit -> Two consecutive left turns after toll -> Precede 4km Turn left at Kyung Hee University
From Yongin-Suseo Express Way
-> Cheongmyeong Exit -> Right turn at Hagal intersection -> 1.5km to turn left to Kyung Hee University
2. By Subway
Off at Suwon station of red line (line number 1), and take any bus of 5, 7, 7-2, 310, 900.
Bus brings you to Kyung Hee University in 30 minutes.
3. Inter-city Buses from Subway Stations in Seoul
Yangjae Station(#3): 5100, 1550-1, Gangbyeon Station(#2): 1112,
Jamsil Station(#2): 1112, 1007-1, Sadang Station(#2 & #4): 7000
4. Suwon City Bus
#5, #7, #7-2, #9, #34, #116-3, #310, #900